1. Field of the Invention
The present invention is related to a semiconductor package in which a semiconductor die is disposed between upper and lower plate members and, more particularly, to an S08 semiconductor package in which a source of a MOSFET semiconductor die is electrically coupled to a leadframe via an upper plate member while the MOSFET gate is electrically coupled to the leadframe via a wire bond.
2. Related Art
With reference to FIG. 1, a semiconductor package 10 according to the prior art is shown. The semiconductor package 10 includes a bottom plate portion 13 and terminals 12a, 12b. A semiconductor die 16 is disposed on top of the bottom plate portion 13 and fastened thereto, typically using an epoxy material. The semiconductor die 16 includes a metalized region 18 (typically aluminum) defining a connection area for a top surface of the semiconductor die 16. Portions of the terminals 12a, 12b, bottom plate portion 13, and semiconductor die 16 are encapsulated in a housing 22, typically formed from a moldable material. In order to obtain an electrical connection between the metalized region 18 and the terminal(s) 12b, one or more wires 20 are ultrasonically bonded at one end 21a to the metalized region 18 and at a distal end 21b to the terminal 12b.
FIG. 2 shows another semiconductor package 100 of the prior art. In order to electrically connect the metalized region 18 with the terminal 12b, one or more wires 24 are stitch bonded at locations 23, thereby providing additional paths for current to flow from the semiconductor die 16 to the terminal 12b. This marginally reduces the resistance of the current path from the semiconductor die 16 to the terminal 12b.
It is desirable to significantly reduce the resistance and inductance of current paths through a power semiconductor package in order to ensure optimum performance of the semiconductor device. Unfortunately, the semiconductor packages of the prior art do not fully achieve this objective because, among other things, the distance D between one area of the metalized region 18 and the end 21a of the wires 20 increases the resistance of the current path from the metalized region 18 to the terminal 12b. This problem is exacerbated when the thickness of the metalized region 18 is relatively small (typically, the thickness is approximately 4 to 8 microns). The relatively thin metalized region 18 in combination with the distance D and the cross sectional profile of the wire bond 20 results in a relatively high resistance and inductance for the current path therethrough.
In some packages (for example S08 packages) the distance D is approximately 80 to 100 mils resulting in a resistance of between about 0.79 and 1.58 mohms for the metalized region 18. The diameters of the wires 20, 24 are approximately 2 mils yielding resistances of about 1.05 mohms (when 14 wires are used). With terminal and epoxy resistances aggregating to about 0.307 mohms, such packages exhibit total resistances of between about 2.14 to 2.93 mohms. The resulting package thermal resistance, RJA, can reach 62.5.degree. C./W.
When the semiconductor package 10 includes, for example, a MOSFET semiconductor die 16, the resistance caused by the distance D and the relatively small diameter of the wires 20, 24 adds to the overall resistance of the MOSFET. Indeed, when die 16 is a MOSFET die, the terminals 12a are typically coupled to the drain of the MOSFET while the terminals 12b are coupled to the source of the MOSFET via one or more wire bonds 20. As ON resistances of MOSFET dies become smaller and smaller, the resistance caused by the distance D and the wire bonds 20, 24 become a larger and larger portion of the overall resistance from one terminal 12a to another terminal 12b. Of course, the high frequency performance of a semiconductor device, like a MOSFET, is significantly effected by the resistance and inductance from terminal to terminal through the device.
Some prior art packages have incorporated a large metal strap to obtain an electrical connection between the metalized region 18 and terminal 12b. Unfortunately, this technique has only been possible in large semiconductor packages having relatively simple surface structures, such as bipolar junction transistors, diodes, and thyristors. Further, the metal straps were not practical in small outline packages (such as S08, surface mount dual in line packages).
The use of a large metal strap in a MOS-gated device, such as a MOSFET, has not heretofore been achieved because such devices have relatively complex surface structures. In particular, MOS-gated devices typically include a gate runner (or bus), disposed on the surface of the semiconductor die, which traverses the surface such that gate potential is distributed over the surface of the die. Consequently, disposing a large metal strap over the surface of the die has been problematic because the gate runner restricts access to the die surface and could be shorted to the metal strap. Thus, the use of metal straps in MOS-gated semiconductor devices has been prohibitive.
Accordingly, there is a need in the art for a new semiconductor package which overcomes the deficiencies in the prior art semiconductor packages by, among other things, reducing the resistances of the current paths through MOS-gated devices and reducing the inductances of such current paths.